|Port Type||Name||Width (bits)||Description|
This page provides detailed information about the SystemC TLM2 Fast Processor Model of the Renesas RL78-S1 core.
Processor IP owner is Renesas (formerly NEC).
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.
The model has been run through an extensive QA and regression testing process.
This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.
Model downloadable (needs registration and to be logged in) in package rl78.model for Windows32 and for Linux32. Note that the Model is also available for 64 bit hosts as part of the commercial products from Imperas.
Model Variant name: RL78-S1
RL78 Family Processor Model.
Open Source Apache 2.0
RL78 User Manual: Software, Single-Chip microcontrollers, http://documentation.renesas.com/doc/products/mpumcu/doc/rl78/r01us0015ej0220_rl78.pdf
All instructions are supported except the MULU, MULHU, MULH, DIVHU, MACHU and MACH instructions that are not implemented.
Banked registers are not supported
The PMC (Processor Model Control) register behavior is not modeled.
This processor model requires that RAM is available at the address range of the memory mapped registers
Address ranges 0xFFEE0 to 0xFFEFF for General purpose registers (e.g. X, A)
Address ranges 0xFFFF0 to 0xFFFFF for special function registers (e.g. SP)
This processor model should be started with a reset signal. The processor reads from the reset vector 0x0000 on reset and uses this value for the initial PC
Models have been tested by eSOL TRINITY and Imperas
External exceptions are supported
The BRK instruction (internal trap) is supported
Memory mirroring is supported
Memory mapped registers is supported
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32. Note that the simulator is also available for 64 bit hosts as part of the commercial products from Imperas.
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant RL78-S1 is available OVP_Model_Specific_Information_rl78_RL78-S1.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: renesas.ovpworld.org/processor/rl78/1.0
Processor Endian-ness: This model is little endian.
Processor ELF Code: The ELF code for this model is: 0xc5
QuantumLeap Support: The processor model has not yet been qualified to run in a QuantumLeap enabled simulator.
The RL78-S1 SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_rl78_RL78-S1.pdf.
Information on the RL78-S1 OVP Fast Processor Model can also be found on other web sites::
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.imperas.com has more information on the model library
http://www.ovpworld.org: iGen Peripheral Generator User Guide
http://www.ovpworld.org: Describes a methodology to extend the base RISC-V Processor model for custom instructions, CSRs, Exc
http://www.ovpworld.org: riscvOVPsim. A complete RISC-V ISS for bare-metal software development and Specification Compliance Test Development
http://www.ovpworld.org: Altera Nios II Bare Metal & Cyclone III Linux Booting Demo Video
Currently available Fast Processor Model Families.